1. Field of the Invention
The present invention relates to a semiconductor device, and in particular to a semiconductor device for generating internal voltage through pumping operation. Specifically, the present invention relates to a substrate bias voltage generating circuit for generating bias voltage to be applied to a substrate region.
2. Description of the Background Art
A semiconductor device is provided with an internal voltage generating circuit in order to reduce power consumption of a whole system and to generate a voltage at a desired level. Internal voltage is classified into a high voltage higher than an external power supply voltage, a reference voltage at a level between the ground voltage and the power supply voltage, a negative bias voltage applied to a substrate region of the semiconductor device, and so on. Particularly in a semiconductor memory device, a bias voltage VBB is applied to the substrate region in order to stabilize the threshold voltage of memory cell transistors composed of MOS transistors (insulated gate type field effect transistors) and to reduce the junction capacitance thereof.
FIG. 14 is a block diagram schematically showing a conventional bias voltage generating circuit. In FIG. 14, the bias voltage generating circuit includes an active bias voltage generating circuit activated in an active cycle 102 for generating the bias voltage VBB, a standby bias voltage generating circuit 104 for generating the bias voltage VBB in a standby cycle, and a level detecting circuit 100 for detecting whether or not the level of the bias voltage VBB reaches a predetermined voltage level to selectively activate, according to the detection result, the active bias voltage generating circuit 102 or the standby bias voltage generating circuit 104. This level detecting circuit 100 includes a level detector for the active cycles and a level detector for the standby cycles, which generate active activity control signal xcfx86AL and standby activity control signal xcfx86SL, respectively. The bias voltage VBB is a negative voltage. If this bias voltage VBB drops below a predetermined value, the level detecting circuit 100 stops the bias voltage generating operation of the bias voltage generating circuit(s) 102 and/or 104.
The active bias voltage generating circuit 102 has a large charge supply capability and prevents fluctuation in the level of the bias voltage VBB in the operation of an internal circuit in an active cycle. The standby bias voltage generating circuit 104 has a relatively small charge supply capability, and suppresses fluctuation in the bias voltage VBB due to a leakage current in a standby state.
The active bias voltage generating circuit 102 includes an active ring oscillator 102a that performs oscillation operation selectively, dependently on the activity control signal xcfx86AL from the level detecting circuit 100, and an active pumping circuit 102b that utilizes a charge pumping operation of a capacitor and supplies charges to an output node, dependently on an oscillation signal from the active ring oscillator 102a. When the activity control signal xcfx86AL is in an active state and instructs that the bias voltage VBB does not reach a predetermined voltage level, the active ring oscillator 102a performs oscillation operation. When the bias voltage VBB reaches the predetermined level, the oscillator 102a stops the oscillation operation.
The standby bias voltage generating circuit 104 includes a standby ring oscillator 104a that performs oscillation operation selectively, dependently on the activity control signal xcfx86SL from the level detecting circuit 100, and a standby pumping circuit 104b that performs a charge pumping operation through a capacitor and generates the bias voltage VBB, dependently on an oscillation signal from the standby ring oscillator 104a. When the activity control signal xcfx86SL instructs that the bias voltage VBB does not reach a predetermined voltage level, the standby ring oscillator 104a also performs oscillation operation. When the activity control signal xcfx86SL instructs that the bias voltage VBB reaches the predetermined level, the oscillator 104a stops the oscillation operation.
By providing a bias voltage generating circuit for each of an active cycle and a standby cycle, the operation of the active bias voltage generating circuit 102, which has a large charge supply capability, is stopped in a standby cycle to reduce power consumption. The active pumping circuit 102b and the standby pumping circuit 104b utilize charge pumping operation of capacitors. The capacitance values of these capacitors are different from each other and the charge supply capability of the standby pumping circuit 104b is made smaller. In the charge pumping circuit utilizing the charge pumping operation of a capacitor, its charge supply capability is proportional to the frequency of an oscillation signal and the capacitance of the capacitor that performs the charge pumping operation.
A charge pumping circuit utilizing a capacitor can be formed into various structures. Typical examples of the charge pumping circuit. structure are a single boost type charge pumping circuit and a double boost type charge pumping circuit.
FIG. 15 is a block diagram showing a conventional single boost type charge pumping circuit. In FIG. 15, the single boost type charge pumping circuit includes: an inverter circuit IV1 receiving a clock signal CLK from a ring oscillator; a delay circuit DL1 for delaying an output signal of the inverter circuit IV1; a delay circuit DL2 for delaying an output signal of the delay circuit DL1 further; a NOR gate NG1 receiving output signals of the delay circuits DL1 and DL2; a NAND circuit NG2 receiving the output signal of the inverter circuit IV1 and the. output signal of the delay circuit DL2; a NOR gate NG3 receiving the output signals of the inverter circuit IV1 and the delay circuit DL1; a delay circuit DL3 for delaying the output signal of the NOR gate NG1; a buffer circuit DL4 for delaying the output signal of the NAND circuit NG2; an inverter IV2 for inverting the output signal of the NOR gate NG3; a capacitor Clhavingone electrode node coupled to receive the output signal of the delay circuit DL3; a capacitor C2 having one electrode node coupled to receive the output signal of the delay circuit DL4; a capacitor C3 having one electrode node coupled to receive an output signal of the inverter circuit IV2; a P channel MOS transistor Q1 connected between the other electrode node (node NF) of the capacitor C3 and the ground node; P channel MOS transistors Q2 and Q3 connected in series between the node NF and the ground node; a P channel MOS transistor Q4 connected between the other electrode node (node NB) of the capacitor C1 and the ground node and having a gate connected to the node NF; a P channel MOS transistor Q5 connected between the other electrode node (node NE) of the capacitor C2 and the ground node and having a gate connected to the node NF; and a P channel MOS transistor Q6 made conductive selectively, depending on the voltage level of the node NE, to transfer charges between the nodes ND and NO.
P channel MOS transistor Q1 has a gate connected to the ground node so that the transistor Q1 operates in a diode mode to damp the voltage level of the node NF to an absolute value Vthp of its threshold voltage. The MOS transistors Q2 and Q3 each are diode-connected in the forward direction from the ground node to the node NF, so that the voltage level of the node NF is damped on xe2x88x922xc2x7Vthp, wherein Vthp represents the absolute value of the threshold voltage of each of Q1 to Q3. Now, the description will be made of the operation of the single boost type charge pumping circuit shown in FIG. 15.
Suppose such initial state that nodes NA-NF are at a level of the ground voltage Vss (=0V) and the clock signal CLK rises up to an H level. In this case, the output signal of the inverter circuit IV1 falls to an L level. The voltage of the node NB rises to the power supply voltage Vcc after the passage of the delay time of the delay (buffer) circuit DL4. When the delay times of the delay circuits DL1 and the DL2 pass, two inputs of the NOR gate NG1 are at an L level. When the delay time of the delay circuit DL3 passes further, the voltage level of the node NA rises to the level of the power supply voltage Vcc.
The node NC is at a voltage level of 0 V in the initial state. Then the node NC rises in voltage to an H level as the power is on. After the passage of the delay time of the delay circuit DL1, the node NC is driven to the ground voltage level by the inverter circuit IV2 because the NOR gate NG3 receives the L-level signals at both inputs to output an H-level signal. Responsive to the rise in the voltage of the node NA, the voltage level of the node ND is going up toward the power supply voltage Vcc, through the charge pumping operation of the capacitor C1. However, the voltage level of the node NF is at the ground voltage level and the MOS transistor Q4 is in an on-state, so that the voltage level of the node ND is lowered until the MOS transistor Q4 turns off. In a similar way, the voltage level of the node NE is going up toward the power supply voltage Vcc through the charge pumping operation of the capacitor C2. However, the MOS transistor Q5 is in an on-state, and the voltage level at the node NE falls until the MOS transistor Q5 turns into an off-state.
When the clock signal CLK falls from the power supply voltage Vcc level to the ground voltage, the output signal of the inverter circuit IV1 changes to a level of the power supply voltage Vcc so that the output signal of the NOR gate NG3 changes to the L level (the ground voltage level). The voltage level of the node NC attains the power supply voltage Vcc level by the inverter circuit IV2. The voltage level of the node NF is to be raised by the charge pumping operation of the capacitor C3 accordingly. However, in response to on the rise in the voltage of the node NF, the MOS transistor Q1 turns on so that the voltage level of the node NF is clamped at the absolute value Vthp of its threshold voltage. When the voltage of the node NF is clamped at the absolute value Vthp of the threshold voltage, the MOS transistors Q4 and Q5 turn off (since the nodes ND and NE are discharged to a level near the ground voltage).
Subsequently, the output signal of the delay circuit DL1 rises to the power supply voltage level, so that the output signal of the NOR gate NG1 falls to the ground voltage level. After the passage of the delay time of the delay circuit DL3, the voltage of the node NA falls from the power supply voltage Vcc level to the ground voltage level. By the charge pumping operation of the capacitor C1, the voltage level of the node ND falls to a level of xe2x88x92Vcc.
When the delay times of the delay circuits DL1 and DL2 pass, the output signal of the NAND gate NG2 changes to the L level and the voltage level of the node NB falls from the power supply voltage Vcc to the ground voltage level. The voltage level of the node NE drops to a level of xe2x88x92Vcc accordingly. When the voltage level of the node NE drops substantially to a level of xe2x88x92Vcc, the MOS transistor Q6 turns on because the output node NO is at a level near to the ground voltage in the initial state, and negative charges (electrons) are supplied from the node ND to the output node NO.
Next, the clock signal CLK rises up again to the power supply voltage Vcc level, so that the node NB changes from the ground voltage level to the power supply voltage Vcc level. Accordingly, the voltage level of the node NE rises, by Vcc, by the charge pumping operation of the capacitor C2 so that the MOS transistor Q6 turns off. Thus, the supply of the negative charges to the output node NO is stopped.
Subsequently, the output signal of the delay circuit DL1 is changed to the ground voltage level, so that the voltage level of the node NC falls from the power supply voltage Vcc level to the ground voltage level. The voltage of the node NF is to be lowered, by the power supply voltage Vcc, by the charge pumping operation of the capacitor C3. However, the voltage of the node NF is clamped on a voltage level of xe2x88x922xc2x7Vthp through the MOS transistors Q2 and Q3.
Thereafter, the output signal of the delay circuit DL2 is changed to the L level, so that the voltage of the node NA rises from the ground voltage level to the power supply voltage Vcc level and charges are supplied to the node ND accordingly. However, the MOS transistor Q4 is in an on-state and the voltage of the node ND is kept at the ground voltage level.
By repeating the above-mentioned operation, the level of the voltage VBB from the output node NO is lowered. The operation when this state is repeated to attain a stationary state will be described, referring to a waveform diagram of FIG. 16.
The clock signal CLK rises up initially to the power supply voltage Vcc level at time (ta), so that the nodes NA and NB are at the ground voltage level, the node NC is at the power supply voltage Vcc level and the node NE is at a level of xe2x88x92Vcc.
When the delay time of the delay circuit DL4 passes after the clock signal CLK rises up to the power supply voltage Vcc level at time ta, the voltage level of the node NB rises to the power supply voltage Vcc level at time tb. Accordingly, the voltage level of the node NE rises from xe2x88x92Vcc to the ground voltage level and the MOS transistor Q6 turns off.
Subsequently, when the delay time of the delay circuit DL1 passes and two inputs of the NOR gate NG3 change to the L level at time tc, the voltage level of the node NC falls from the power supply voltage Vcc level to the ground voltage level. Subsequently, the voltage level of the node NF also falls by the power supply voltage Vcc level. The voltage of the node NF is clamped on the absolute value Vthp of a threshold voltage by the MOS transistor Q1. Therefore, the voltage level of the node NF drops toward a voltage level of Vthpxe2x88x92Vcc, but the voltage level thereof is clamped on xe2x88x922xc2x7Vthp by the MOS transistors Q2 and Q3. In response to the fall of the voltage level of the node NF, the MOS transistors Q4 and Q5 turn on to hold the voltage of the node NE reliably at the ground voltage level. Consequently, the MOS transistor Q6 turns off so that the operation of supplying electrons to the output node NO is stopped. This node ND is fixed to the ground voltage level by the MOS transistor Q4 that is in an on-state (In FIG. 16, delay of response is shown).
When the delay times of the delay circuits DL1-DL3 pass, the voltage level of the node NA rises to the power supply voltage Vcc level. Even if the voltage level of the node ND is going to rise, the MOS transistor Q4 is in an on-state so that the voltage of the node ND is kept at the ground voltage level.
When the clock signal CLK falls to the ground voltage level at time te, the voltage level of the node NC rises to the power supply voltage Vcc level first. The voltage level of the node NF rises accordingly, and is clamped on the voltage Vthp level by the MOS transistor Q1 (time tf).
Subsequently, when the delay times of the delay circuits DL1 and DL3 pass, the voltage level of the node NA falls to the ground voltage level at time tg. The voltage level of the node ND falls to a level of xe2x88x92Vcc accordingly. The voltage level of the node NE is the ground voltage and the MOS transistor Q6 is kept in the off-state.
Furthermore, when the delay time of the delay circuit DL2 passes and the voltage level of the node NB falls to the ground voltage level at time th, the voltage level of the node NE changes to a level of xe2x88x92Vcc responsively. Moreover, the MOS transistor Q6 turns on, and negative charges are supplied to the output node NO so that the voltage level of the node ND rises correspondingly to the supply of the negative charges.
Therefore, in the single boost type charge pumping circuit shown in FIG. 15, the voltage at the gate (node NE) of the MOS transistor Q6, which is a transfer gate for supplying negative charges to the output gate, changes with an amplitude of the power supply voltage Vcc. Such a circuit is called the single boost type on the basis of this voltage amplitude.
By three-phase-driving the nodes NA-NC, the following operations are successively and precisely carried out: preparation of negative voltage in the node ND, supply of negative charges after stabilization of the negative voltage, and preparatory arranged of a negative charge supplying node after the stop of the supply of the negative charges. Thus, the negative charges can be effectively supplied.
FIG. 17 is a block diagram showing a main portion of a double boost type charge pumping circuit. This block shown in FIG. 17 corresponds to the block represented by the alternate long and short dash line in the single boost type charge pumping circuit in FIG. 15, that is, the portion for receiving the output signal of the NAND circuit NG2 to drive the node NE. That is, by replacing the alternate long and short dash line block in FIG. 15 by the block of the circuit shown in FIG. 17, the charge pumping block shown in FIG. 15 operates as a double boost type charge pumping circuit.
In FIG. 17, the double charge type charge pumping circuit includes an inverter circuit DIV3 for driving a node NG in accordance with the output signal of the NAND gate NG2, a delay circuit DL5 for driving a node NH in accordance with the output signal of the NAND gate NG2, an inverter circuit DIV4 for driving a node NI in accordance with the output signal of the NAND gate NG2, a capacitor C4 connected between the node NG and a node NJ, a capacitor C5 connected between the node NH and a node NK, an N channel MOS transistor NQ4 for connecting a power node to the node NK in accordance with the voltage on the node NJ, an N channel MOS transistor NQ1 connected between the node NJ and the power node, and N channel MOS transistors NQ3 and NQ2 connected in series between the power node and the node NJ.
MOS transistor NQ1 has a back gate and a gate connected together to the power node. Each of MOS transistors NQ2 and NQ3 has a back gate connected to the power node, and a gate connected to a source thereof. MOS transistor NQ1clamps the voltage level of the node NJ at a level of Vccxe2x88x92Vthn. MOS transistors NQ3 and NQ2 clamps the voltage level of the node NG at Vcc+2xc2x7Vthn, where Vthn is the threshold value of each of the MOS transistors NQ1 to NQ3.
Each of the inverter circuits DIV3 and DIV4 has a delay time. The double boost type charge pumping circuit further includes a P channel MOS transistor PQ for supplying charges at the node NK to a node NL in accordance with the output signal of the inverter circuit DIV4, and N channel MOS transistors NQ5 and NQ6 connected in series between the node NL and the ground node. MOS transistor NQ5 has a gate coupled to receive the power supply voltage Vcc, to function as a resistor for relaxing the electric field. MOS transistor NQ6 has a gate coupled to receive the output signal of the inverter circuit DIV4. A capacitor C6 is connected between the nodes NL and NE.
FIG. 18 is a waveform diagram representing the operation of the double boost section shown in FIG. 17. Referring to FIG. 18, the description will now be made of the operation of the circuit shown in FIG. 17.
The inverter circuit DIV3 has a larger delay time than the inverter circuit DIV4 has. The delay circuit DL5 has a larger delay time than the inverter circuits DIV3 and DIV4 have.
Signal xcfx86 from the NAND gate NG2 rises up to the power supply voltage Vcc level at time Ta. When the delay time of the inverter circuit DIV4 passes, the voltage level of the node NI falls from the power supply voltage Vcc level to the ground voltage level, so that the MOS transistor PQ turns on and the MOS transistor NQ6 turns off. The voltage on the node NK transmits to the node NL accordingly. The node NK is at the power supply voltage Vcc level. At time Tb, the voltage level of the node NL rises to the power supply voltage Vcc level. The voltage level of the node NE rises by the power supply voltage Vcc level accordingly, so as to change to a level of xe2x88x92Vcc.
When the delay time of the inverter circuit DIV3 passes, the voltage level of the node NG falls down to the ground voltage level at time Tc. The voltage of the node NJ is going to change by the power supply voltage Vcc level accordingly. However, the voltage level of the node NJ is clamped by the MOS transistor NQ1, to drop to a voltage level of Vccxe2x88x92Vthn. When the voltage level of the node NJ attains a level of Vccxe2x88x92Vthn, the MOS transistor NQ4 turns off.
At time Td, the delay time of the delay circuit DL5 passes, and the voltage level of the node NH attains the power supply voltage Vcc level. As a result, the voltage level of the node NK rises from the power supply voltage Vcc level to 2xc2x7Vcc by the charge pumping operation of the capacitor C5. The voltage level of the node NL rises to 2xc2x7Vcc accordingly. By the capacitor C6, the voltage level of the node NE rises by the power supply voltage Vcc and the voltage level of the node NE attains the ground voltage level.
The signal xcfx86 from the NAND gate NG2 falls to the ground voltage level at time Te. As a result, the voltage level of the node NI attains the Vcc level at time Tf by the inverter circuit DIV4 so that MOS transistor NQ6 turns on. Charges of the node NL are discharged accordingly, so that the node NL attains the ground voltage level. The voltage level of the node NI rises from the ground level to the power supply voltage Vcc, so that the voltage level of the node NK is 2xc2x7Vcc and MOS transistor PQ is in an on-state. Therefore, charges are discharged from the node NK to the ground node through the MOS transistor PQ and the MOS transistor NQ6. The voltage level of the node NK drops to the power supply voltage Vcc by the discharge, so that the voltage levels of the gate and the source of the MOS transistor PQ become equal so that the MOS transistor turns off. Therefore, the discharging continues until the voltage level of the node NK drops from 2xc2x7Vcc to the power supply voltage Vcc.
The voltage of the node NE drops to xe2x88x922xc2x7Vcc in response to the drop in the voltage level of the node NL.
At time Tg, the voltage level of the node NG rises to the power supply voltage Vcc, and the voltage level of the node NJ rises by the charge pumping operation of the capacitor C4. However, the voltage level of the node NJ is clamped on a level of Vcc+2xc2x7Vthn by the MOS transistors NQ2 and NQ3. The node NK is at a voltage level of 2xc2x7Vcc and the MOS transistor NQ4 is kept in an off-state.
At time Th, the voltage level of the node NH drops from the power supply voltage Vcc to the ground voltage level, in accordance with the output signal of the delay circuit DL5. At the above-mentioned time Tg, the voltage of the node NJ is already set to a level higher than the power supply voltage and the N channel MOS transistor NQ4 is in an on-state. This node NK is connected to the power node through the N channel MOS transistor NQ4. Therefore, the charges supplied from the power node compensate for the drop in the voltage of the node NK by the charge pumping operation of the capacitor C5, so that the voltage level of the node NK is kept at the power supply voltage Vcc level.
Accordingly, in the double boost section shown in FIG. 17, the amplitude of the voltage at the node NE is 2xc2x7Vcc. The circuit of this type is called the double boost type. In the double boost type charge pumping circuit, the gate-source voltage of the MOS transistor Q6, which supplies charges, becomes large, so that its charge supply capability also becomes large. Therefore, charges can be supplied at a higher speed.
The number of constituent elements of the single boost type charge pumping circuit is smaller than that of constituent elements of the double boost type charge pumping circuit. Thus, the single type has advantages that its circuit occupation area is small and that because of its simple circuit structure its reliability and yield are high. However, the gate voltage of the transistor Q6 for transferring charges can be driven to xe2x88x92Vcc at lowest, and the negative voltage that can be generated is xe2x88x92Vcc+Vthp. Thus, a negative voltage having a sufficient voltage level can not be generated. In the case where the power supply voltage Vcc and the absolute value Vthp of the threshold voltage are, for example, 1.5 V and 0.7 V, respectively, more negative voltages than xe2x88x920.8 V cannot be generated.
On the other hand, in the case of the double boost type charge pumping circuit, the gate voltage of the transistor Q6 for transferring charges drops down to xe2x88x922xc2x7Vcc. It is therefore possible to generate and supply a negative voltage having a sufficient voltage level stably even under any low power supply voltage. In the double boost section shown in FIG. 17, however, the voltage of its internal node changes with an amplitude of 2xc2x7Vcc. Therefore, in the case where the power supply voltage Vcc is high, the reliability of the element (the reliability of the gate insulating film) drops, so that a problem that the power supply voltage cannot be made high arises. Therefore, in the case that the power supply voltage level is high, it is necessary that the voltage down converted by an internal voltage down converter is used as pumping power supply voltage. Thus, only a negative voltage having a level similar to that generated in the single boost type circuit can be generated. In short, the advantage of the double boost type is lost. In the case that the internal voltage down converter is provided for substrate bias, a problem that the occupation area of this circuit and the power consumption increase arises.
In the test (the screening test) of a semiconductor device, the device is operated under various power supply voltage levels to detect a failure. When the double boost type charge pumping circuit is used in this test, its highest power supply voltage level is limited by the dielectric breakdown voltage of elements of its double boost section, so that applied voltage cannot be made adequately high. Thus, the reliability of its internal circuit cannot be guaranteed sufficiently. In the case that the power supply voltage of the single boost type charge pumping circuit is made low, a negative voltage VBB having an adequate voltage level cannot be generated, so that the operation of its internal circuit cannot be stabilized. Thus, the test cannot be precisely made. Therefore, there arise problems that the test is insufficient and the reliability and the yield of the semiconductor devices drop.
Accordingly, in the case that a charge pumping circuit for substrate bias is mounted on a semiconductor chip, after due consideration of its specification it is decided which type of the charge pumping circuit is used dependently on the power supply voltage level of the specification. Thus, it is necessary to change circuit design whenever the specification is changed. Thus, there arises a problem that it becomes impossible to cope with the change in the specification flexibly. The power supply voltage of the charge pumping circuit is mainly decided by the power supply voltage of the system in which the semiconductor memory device is used. Thus, in the case that the charge pumping circuit is designed dependently on use thereof, it is necessary to change the design of the circuit dependently on the specific power supply voltage. Thus, the efficiency of the design is lowered, to result in a problem that costs of the devices rise.
The above-mentioned problems occur not only in the charge pumping circuit for generating a negative voltage but also in an internal voltage generating circuit for generating a high voltage transmitted to word lines in a semiconductor memory device and such.
An object of the present invention is to provide a semiconductor device capable of generating an internal voltage having a desired voltage level stably, regardless of the voltage level of a power supply voltage.
Another object of the present invention is to provide a semiconductor device adaptable with change in the specification of an external power source easily.
A further object of the present invention is to provide a semiconductor device having improved reliability and yield.
A still further object of the present invention is to provide a semiconductor device capable of generating a substrate bias voltage stably and effectively.
The semiconductor device according to an aspect of the present invention includes a first internal voltage generating circuit in a first operation mode for generating an internal voltage at a predetermined voltage level, and a second internal voltage generating circuit, having a second operation mode that is different from said first operation mode, for generating internal voltage having said predetermined voltage level. The first internal voltage generating circuit and the second internal voltage generating circuit can operate selectively.
The semiconductor device according to another aspect of the present invention includes an internal voltage generating circuit for applying a control signal having a first amplitude to a control gate of a transfer gate for transferring charges to an output node, to generate, at the output node, an internal voltage having a voltage level whose maximum absolute value is defined by the amplitude of the control signal; and a circuit for changing the amplitude of the control signal of the internal voltage generating circuit into a second amplitude different from the first amplitude in response to a switch signal.
The semiconductor device according to further aspect of the present invention includes an internal voltage generating circuit for applying a control signal to a control gate of a transfer gate for transferring charges to an output node, to generate, at the output node, an internal voltage having a predetermined voltage level; and a circuit for setting the amplitude of the control signal of the internal voltage generating circuit to either of a first amplitude and a second amplitude which is smaller than the first amplitude, in response to a switch signal.
Preferably, there are arranged a single boost type substrate bias generating circuit for generating a bias voltage applied to a substrate region through charge pumping operation; and a double boost type substrate bias generating circuit for generating a bias voltage applied to the substrate region through charge pumping operation. The double boost type substrate bias generating circuit is mounted, together with the single boost type substrate bias generating circuit, on a common semiconductor chip. In a practical use, either one of the single boost type substrate bias generating circuit and the double boost type substrate bias generating circuit can be used.
By selectively operating the internal voltage generating circuits having different operation modes prepared together, it is possible to use the optimal internal voltage generating circuit dependently on the voltage level of an external power source, and change in the specification of the power source can be coped with flexibly. In a test, by allowing the internal voltage generating circuit suitable for a test power supply voltage level to operate, the internal circuitry can be precisely tested to improve reliability and yield.
Regardless of a voltage level of an external power source, internal voltage can be generated using the external power source. Thus, it becomes unnecessary to use any internal voltage down converter for generating an internal voltage, and it also becomes possible to reduce power consumption.
By forming the internal voltage generating circuits in the different operation forms in the same circuit, their constituent elements can be made common. In this case, the occupation area of the internal voltage generating circuitry can be made smaller than in the case that these circuits are separately. formed.
In the case that this internal voltage generating circuit is a substrate bias generating circuit, substantially the same advantages can be obtained.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.